Visibl Semiconductors
Product & Competitive Intelligence
AI coordination layer for chip design that detects drift, proposes fixes, and surfaces tapeout risk.
Company Overview
Builds an AI-powered coordination layer for chip design that uses autonomous agents to detect design drift, auto-triage issues, propose verified fixes, and surface tapeout-risk insights to executives.
Competitive Advantage & Moat
Product Roadmap & Public Announcements
Visibl has publicly described a four-layer product: (1) continuous monitoring of specs, RTL, and CI for design drift, (2) automated case generation with supporting evidence, (3) AI-proposed and verified fix diffs packaged for human review, and (4) executive dashboards showing readiness, schedule impact, and tapeout risk. Their website positions the platform as an integration layer that sits atop existing EDA and CI toolchains rather than replacing them.
Signals & Private Analysis
Job postings and GitHub activity remain minimal, consistent with a two-person founding team still in stealth-to-launch mode inside YC W26. The CTO's Google Scholar profile and prior work at Arm and Intel on ML-for-hardware suggest the team is building proprietary models trained on RTL and verification corpora. Conference and community signals hint at early design-partner conversations with fabless semiconductor companies frustrated by late-stage respins. Expansion into automated verification sign-off and physical-design optimization is a logical next step given the founders' backgrounds.
Product Roadmap Priorities
AI agents continuously monitor specifications, RTL code, and CI results to detect design drift before it causes costly late-stage chip respins.
Think of it as a spell-checker that constantly compares what the chip blueprint says versus what the engineers actually built, and flags every mismatch instantly.
It's like having a GPS that yells "recalculating!" the moment your chip design takes a wrong turn, instead of letting you drive 200 miles in the wrong direction.
AI agents propose code-level fixes for detected design issues and formally verify them, packaging review-ready diffs for human approval.
It's like an auto-mechanic robot that not only tells you what's wrong with your car but also hands you the exact replacement part, pre-tested and ready to install.
It's like autocorrect for chip design—except it actually runs the spell-check, grammar-check, and fact-check before suggesting the fix.
ML-powered dashboards aggregate signals across the entire design organization to give executives real-time tapeout readiness scores and schedule-impact predictions.
It's a weather forecast for your chip project—instead of guessing if tapeout will be sunny or stormy, executives get a data-driven probability with a five-day outlook.
It's like replacing the "Are we going to make it?" gut check at every staff meeting with an actual scoreboard that updates in real time.
Company Overview
Key Team Members
- Bryce Neil, Co-Founder & CEO
- Jordon Kashanchi, Co-Founder & CTO
Founder Force Multiplier
Jordon Kashanchi built silicon at Intel, Arm, and Microsoft and publishes ML-for-hardware research, while Bryce Neil operationalized enterprise AI at Deloitte's OmniaAI practice, together they uniquely understand both the chip-design pain and the AI solution space from the inside.
Funding History
- 2025 | Bryce Neil and Jordon Kashanchi co-found Visibl Semiconductors.
- 2026 | Accepted into Y Combinator Winter 2026 batch.
Competitors
- Traditional EDA Vendors: Synopsys (Fusion Compiler), Cadence (Cerebrus), Siemens EDA (Solido).
- AI-Native EDA Startups: Quilter AI (PCB), Movellus (clock networks), various stealth AI-for-chip startups.
- Project/Workflow Management: Methodics (Perforce), ClioSoft, Jama Connect (requirements traceability).
